Electrostatic discharge (ESD) protection circuits are widely employed in integrated circuits to protect against high voltage spikes that may be applied to pads (also referred to as pins) of an integrated circuit. These high voltage spikes may be caused by discharge of a built-up static charge resulting from human handling of the integrated circuit. ESD protection circuits may be applied to power supply pads, ground pads or input/output pads (including instruction, data and address pads) of integrated circuit devices.
FIG. 1 is a circuit diagram of a conventional ESD protection circuit. As shown in FIG. 1, a conventional ESD protection circuit includes diodes D1-D4 that are connected between first and second pads 1 and 2 on an integrated circuit substrate. As shown in FIG. 1, pad 1 is a first power supply pad Vcc1 and pad 2 is a second power supply pad Vcc2. However, ground pads or input/output pads may also be used. As shown, a plurality of internal circuits 3 and 4 are also connected to the first and second pads 1 and 2 and are protected by the ESD protection circuit.
FIG. 2 is a cross-sectional view of an integrated circuit including conventional ESD protection circuits. In FIG. 2, only one of the conductive paths comprising diodes D1 and D2 is shown. However, the conductive path comprising diodes D3 and D4 is similar.
Referring to FIG. 2, p+ and n+ regions 22 and 24 correspond to the anode and cathode of diode D1 respectively, and p+ and n+ regions 32 and 34 correspond to anode and cathode of diode D2 respectively. The first and second diodes D1 and D2 are contained in respective first and second well regions 20 and 30 in an integrated circuit substrate such as a semiconductor substrate 10. A p-well region 40 is included between first and second regions 20 and 30. P-well region 40 acts as an isolation region between the n-well regions 20 and 30. As shown, the first and second well regions 20 and 30 include respective first and second circumferences or walls. N-type buried layers 12 and 14 are also included in substrate 10 beneath the n-well regions 20 and 30 respectively. As also shown, the first and second diodes are serially connected between the first and second pads 1 and 2 by a conductive line 5.
Conventional ESD protection circuits described in FIGS. 1 and 2 generally operate when the voltages Vcc1 and Vcc2 applied to the power supply pads 1 and 2 are equal to each other. However, when the voltages Vcc1 and Vcc2 are at different levels, power dissipation may be caused due to the formation of parasitic bipolar transistors Q1 and Q2, shown in FIG. 2, or transistors Q3 and Q4 which would be formed by diodes D3 and D4. As shown in FIG. 3, the transistors Q1 and Q2 form a PNP Darlington pair which can produce high amplification.
For example, if Vcc1=5V and Vcc2=6V, the transistors Q1 and Q2 both conduct. Similarly, if Vcc1=6V and Vcc2=5V, transistors Q3 and Q4 both conduct. If the current gains of the transistors Q1 and Q2 are .beta.1 and .beta.2 respectively, the current gain .beta. of the PNP Darlington pair becomes .beta.1-.beta.2. As shown in FIG. 3, if .beta.1=10 and .beta.2=10, then I2, the base current of parasitic transistor Q2=3 mA and I1, the emitter current of transistor Q1 can become 300 mA or more.
This large leakage current can degrade the performance of the ESD protection circuit and can also increase the power dissipation of the integrated circuit. Moreover, the since the lateral resistance of the substrate 10 may vary based on the position thereof, latch-up may be caused by the parasitic components in the integrated circuit substrate 10. Finally, the formation of the parasitic transistors may reduce the effectiveness of the ESD protection circuit itself.